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- W2019596151 abstract "SRAM-based field programmable gate arrays (FPGAs) are vulnerable to soft-error. To improve circuit dependability, various dependable design techniques have been studied. By the same token, evaluation techniques are required to ensure dependability. The most popular evaluation technique is reconfiguration-based fault-injection (FI) analysis. However, most FI analyses are inadequate for the evaluation of a dependable circuit because they don't consider fault accumulation. The critical issue is the reconfiguration time for injecting many faults. This paper presents an FI analysis system using frame-based partial reconfiguration and a bootstrap method to accelerate evaluation. As a result, our system can accelerate FI time by about a factor of 5 ∼ 10 relative to the full-reconfiguration FI system. Further, the number of reconfiguration times is reduced to one out of several dozen by applying the bootstrap method." @default.
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- W2019596151 date "2012-12-01" @default.
- W2019596151 modified "2023-09-24" @default.
- W2019596151 title "Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration" @default.
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- W2019596151 doi "https://doi.org/10.1109/fpt.2012.6412137" @default.
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