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• W2020128764 abstract "As today's integrated circuit (IC) has easily involved millions and even billions of gates, known as very large-scale integration (VLSI), one natural trend is to move such prohibitive in-house design procedure to the low-cost public cloud. However, such a migration is also raising a challenging request on practical and privacy-preserving techniques to safeguard the sensitive IC design data, i.e., the Intellectual Property (IP). In this paper, we initiate the first study along the direction, and present a practical system for privacy-preserving IC timing analysis, which refers to an essential and expensive procedure via repeated evaluations of timing delays on a gate-level circuit. For privacy protection, our system leverages a key observation that many IP blocks are universally reused and shared across different IC designs, and thus only a small portion of critical IP blocks need to be protected. By carefully extracting such critical design from the whole circuit, our system only outsources the non-critical to the public cloud. As such data splitting does not readily facilitate correct timing analysis, we then develop specialized algorithms to enable the public cloud to take only the non-critical and return intermediate results. Such results can later be integrated with critical design by the local server for fast timing analysis. We also propose a heuristic algorithm to considerably reduce the bandwidth cost in the system. Through rigorous security analysis, we show our system is resilient to IC reverse engineering and protects both the critical IP gate-level design and functionality. We evaluate our system over large IC benchmarks with up to a million of gates to show the efficiency and effectiveness." @default.
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• W2020128764 date "2015-04-14" @default.
• W2020128764 modified "2023-09-24" @default.
• W2020128764 title "Enabling IP Protection for Outsourced Integrated Circuit Design" @default.
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• W2020128764 doi "https://doi.org/10.1145/2714576.2714601" @default.
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