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- W2020143609 abstract "We characterized the behavior of transient bit-line current (I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>BL</sub> ) during reading after giving a pre-bias (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>pre</sub> ) to two different cells in 3-D stacked NAND flash memory having poly-Si body. Depending on the dominance of charge trapping in blocking dielectric or the interface between the tunneling oxide and the poly-Si body, opposite behavior was observed. To identify the cause, we systematically analyzed the capture and emission of charges in two trap sites by investigating transient I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>BL</sub> behaviors during reading with various V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>pre</sub> s and fast & pulsed I-Vs. The carrier life time and trap density associated with grain size were extracted to substantiate different trap density with the vertical position of cells." @default.
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- W2020143609 date "2014-06-01" @default.
- W2020143609 modified "2023-10-17" @default.
- W2020143609 title "Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body" @default.
- W2020143609 doi "https://doi.org/10.1109/vlsit.2014.6894348" @default.
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