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• W2020165975 abstract "To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a focus on writes can shorten both read and write average latency, reduce memory power consumption, and improve overall system performance." @default.
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• W2020165975 date "2011-01-01" @default.
• W2020165975 modified "2023-09-27" @default.
• W2020165975 title "Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue" @default.
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• W2020165975 doi "https://doi.org/10.1109/mm.2010.102" @default.
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