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• W2021651623 abstract "Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance." @default.
• W2021651623 created "2016-06-24" @default.
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• W2021651623 creator A5047899047 @default.
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• W2021651623 date "2015-07-01" @default.
• W2021651623 modified "2023-10-16" @default.
• W2021651623 title "TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors" @default.
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• W2021651623 doi "https://doi.org/10.1109/tvlsi.2014.2334136" @default.
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