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- W2021665618 abstract "The Rate Control is included in each video encoder and exhibits high computational complexity. In order to meet hard real time requirements, a hardware implementation is required. In this paper, a high-performance hardware architecture is proposed. Specifically the RC algorithm included in the JM software has been modified at the Basic Unit level to allow an efficient implementation. The modified RC has comparable image quality while achieving the requirements for UHD resolutions." @default.
- W2021665618 created "2016-06-24" @default.
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- W2021665618 date "2014-11-01" @default.
- W2021665618 modified "2023-09-26" @default.
- W2021665618 title "A hardware implementation of the JVT Rate Control for H.264" @default.
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- W2021665618 doi "https://doi.org/10.1109/telfor.2014.7034512" @default.
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