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- W2021702055 abstract "This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%~34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27~4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding." @default.
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- W2021702055 date "2013-09-01" @default.
- W2021702055 modified "2023-09-27" @default.
- W2021702055 title "A high-performance CABAC encoder architecture for HEVC and H.264/AVC" @default.
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- W2021702055 doi "https://doi.org/10.1109/icip.2013.6738323" @default.
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