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- W2021724238 abstract "In this article, a verification methodology for mixed-signal circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits." @default.
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- W2021724238 date "2008-09-01" @default.
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- W2021724238 title "Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking" @default.
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- W2021724238 doi "https://doi.org/10.1016/j.tcs.2008.03.032" @default.
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