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- W2022059095 abstract "In this work, we consider designing high-rate error-control systems for storage devices using MLC NAND flash memories. Traditional systems designed with either a single BCH code or multiple short BCH codes may suffer from high decoding complexity or rate loss due to limited error-correcting capability, respectively. Aiming at achieving a stronger error-correcting capability with much reduced complexity, we propose an error-control system using a concatenation of short BCH codes with iterative decoding strategies. The performance of the proposed coding scheme is thoroughly analyzed and evaluated with computer simulations and a semi-analytic way at a target page-error rate, 10−14, which confirms our claims: the proposed coding scheme achieves good error-performance and complexity tradeoffs as compared to the traditional schemes and is very favorable for implementation." @default.
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- W2022059095 date "2012-06-01" @default.
- W2022059095 modified "2023-09-26" @default.
- W2022059095 title "Concatenated BCH codes for NAND flash memories" @default.
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- W2022059095 doi "https://doi.org/10.1109/icc.2012.6363960" @default.
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