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- W2022158744 abstract "Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible." @default.
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- W2022158744 date "1984-11-01" @default.
- W2022158744 modified "2023-10-14" @default.
- W2022158744 title "Design for Testability for Complete Test Coverage" @default.
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- W2022158744 doi "https://doi.org/10.1109/mdt.1984.5005686" @default.
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