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- W2022167639 abstract "A low temperature resist trimming process with low trimming rate and good uniformity was developed. Wafer chuck temperature in the ashing chamber was adjusted to be 6 °C to achieve low trimming rate and improve process uniformity. Low power oxygen and argon plasma was used for ashing the resist. Resist lines (0.5 μm wide) patterned with a g-line stepper was trimmed down to sub-100 nm widths. The trimming rate was found to be independent of the initial line width and trimming time. A 0.6 μm CMOS process flow with LOCOS and nitride spacer was suitably modified incorporating resist trimming to fabricate NMOSFETs with gate length as small as 95 nm. Since most polymer-based photoresists can be etched in oxygen plasma, the basic technique could be extended to supplement other lithographic processes for channel length scaling." @default.
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- W2022167639 date "2004-09-01" @default.
- W2022167639 modified "2023-10-06" @default.
- W2022167639 title "Sub-100 nm MOSFET fabrication with low temperature resist trimming process" @default.
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- W2022167639 doi "https://doi.org/10.1016/j.tsf.2004.05.021" @default.
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