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• W2022373172 abstract "We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-μm CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11× faster speeds and 1.54× lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics." @default.
• W2022373172 created "2016-06-24" @default.
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• W2022373172 date "2013-01-01" @default.
• W2022373172 modified "2023-10-17" @default.
• W2022373172 title "Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects" @default.
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• W2022373172 doi "https://doi.org/10.1109/ted.2012.2225150" @default.
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