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• W2022532823 abstract "For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of >5.0. The MOM unit capacitance of 3.5 fF/um2 is achieved with only 4 metal layers." @default.
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• W2022532823 date "2007-12-01" @default.
• W2022532823 modified "2023-09-26" @default.
• W2022532823 title "A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM" @default.
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• W2022532823 doi "https://doi.org/10.1109/iedm.2007.4418918" @default.
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