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- W2023030276 abstract "It has recently been shown that for very large chips, especially those with some incorporated redundancy, the chip's floorplan may affect its yield. When selecting a floorplan, the designer should, therefore, consider the expected yield in addition to the traditional objectives such as area, performance, and routing complexity. This paper studies the two seemingly unrelated objectives of routing complexity minimization and yield maximization, and justifies the need for a trade-off analysis when determining the floorplan. We will focus on the analysis of large memory ICs with redundant modules, for which several alternative floorplans may exist." @default.
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- W2023030276 date "1999-04-27" @default.
- W2023030276 modified "2023-09-27" @default.
- W2023030276 title "Floorplanning of memory ICs: routing complexity vs. yield" @default.
- W2023030276 doi "https://doi.org/10.1117/12.346926" @default.
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