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• W2023138935 startingPage "338" @default.
• W2023138935 abstract "In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively" @default.
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• W2023138935 date "2007-03-01" @default.
• W2023138935 modified "2023-10-06" @default.
• W2023138935 title "Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop" @default.
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• W2023138935 doi "https://doi.org/10.1109/tvlsi.2007.893623" @default.
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