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- W2023177003 abstract "This paper presents a digital interpolation chain for non-integer variable-ratio sampling rate conversion, targeted to 4G mobile applications. Such a system is needed in all-digital transmitters, where the sampling rate of the digital input to the RF front-end must be an integer fraction of the carrier frequency. A highly configurable architecture is proposed to cope with the flexibility needed in 4G applications. The system achieves excellent ACLR of 75 dB, EVM degradation of 0.05%, and RX-band noise below −160 dBc/Hz. Digital synthesis of the circuit in a 40nm low-power CMOS process results in a core area of only 0.073 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . The estimated power consumption is between 6 and 29 mW, depending on channel bandwidth and transmission band." @default.
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- W2023177003 date "2013-09-01" @default.
- W2023177003 modified "2023-09-23" @default.
- W2023177003 title "A configurable sampling rate converter for all-digital 4G transmitters" @default.
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- W2023177003 doi "https://doi.org/10.1109/ecctd.2013.6662279" @default.
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