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- W2023321962 abstract "Verification of designs containing pre-designed cores is a challenging topic in modern IC design, since traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. The port order fault model (POF) has recently been introduced for detecting design errors occurring during integration of a core into a system-on-chip or during test logic insertion. In this work, we generate verification patterns with 100% coverage of a sub-class of POF, called 2-POF. We provide theoretical arguments and experimental results backing the efficiency of these patterns also for detecting higher-order POFs. Moreover, verification pattern sets generated by our approach are more compact compared to the results published before." @default.
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- W2023321962 date "2003-06-01" @default.
- W2023321962 modified "2023-09-27" @default.
- W2023321962 title "Pattern-based verification of connections to intellectual property cores" @default.
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- W2023321962 doi "https://doi.org/10.1016/s0167-9260(03)00003-8" @default.
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