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- W2023358263 abstract "This brief describes a new Class D amplifier topology with digital input and a digital compensation loop filter to improve linearity. The core of the system is a high resolution hybrid multi-bit ΣΔ-Pulse Width Modulation (PWM) modulator. The modulator does not require dynamic element matching nor signal processing to correct for distortion arising from the discrete PWM process. A system prototype based on a FPGA and commercial 16b analog to digital converter (ADC) validate the system design before implementation in 0.13µm CMOS. Measurement results at 1kHz yield a Total Harmonic Distortion (THD) better than 0.03% and greater than 30dB of noise rejection and linearity enhancement. The system is inherently scalable to deep submicron processes due to its predominately digital architecture." @default.
- W2023358263 created "2016-06-24" @default.
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- W2023358263 date "2009-06-01" @default.
- W2023358263 modified "2023-09-28" @default.
- W2023358263 title "A low power Class D audio amplifier with discrete time loop filter compensation" @default.
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- W2023358263 doi "https://doi.org/10.1109/newcas.2009.5290462" @default.
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