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• W2023477532 abstract "Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly increasing the effectiveness of multi-site testing. However, TDM suffers from some inherent limitations that do not allow the fullest possible exploitation of TAM bandwidth. To overcome these limitations, we propose space-division multiplexing (SDM), which complements TDM and offers higher multi-site test efficiency. We implement space-and time-division multiplexing (STDM) using a new, scalable test-time minimization method based on a combination of bin packing and simulated annealing. Results for industrial SoCs, highlight the advantages of the proposed optimization method." @default.
• W2023477532 created "2016-06-24" @default.
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• W2023477532 date "2014-03-24" @default.
• W2023477532 modified "2023-10-01" @default.
• W2023477532 title "Multi-site test optimization for multi-V dd SoCs using space- and time- division multiplexing" @default.
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• W2023477532 doi "https://doi.org/10.5555/2616606.2616763" @default.
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