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• W2023487731 abstract "Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the FPGA-based implementation of 2-D convolution with medium–large kernels. It is a multiplierless solution based on Distributed Arithmetic implemented using general purpose resources in FPGAs. Our proposal is modular and coefficient independent, so it remains fully flexible and customizable for any application. The architecture design includes a control unit to manage efficiently the operations at the borders of the input array. Results in terms of occupied resources and timing are reported for different configurations. We compare these results with other approaches in the state of the art to validate our approach." @default.
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• W2023487731 date "2012-09-01" @default.
• W2023487731 modified "2023-10-01" @default.
• W2023487731 title "FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size" @default.
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• W2023487731 doi "https://doi.org/10.1016/j.sysarc.2012.06.002" @default.
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