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- W2023507965 abstract "As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements." @default.
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- W2023507965 date "2006-06-01" @default.
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- W2023507965 title "Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices" @default.
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- W2023507965 doi "https://doi.org/10.1016/j.mejo.2005.07.019" @default.
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