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• W2023590790 abstract "The overall issues and trends in logic MOSFET scaling are discussed from the perspective of the 2003 and 2004 editions of the International Technology Roadmap for Semiconductors. Critical challenges with scaling include managing gate leakage current, polysilicon gate depletion, and short channel effects. Key innovations to address these challenges include high‐k gate dielectric, metal gate electrode, strained silicon channel for enhanced mobility, and eventually, non‐classical CMOS devices (e.g., FinFETs). These innovations will present significant metrology and characterization challenges as well." @default.
• W2023590790 created "2016-06-24" @default.
• W2023590790 creator A5060203468 @default.
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• W2023590790 date "2005-01-01" @default.
• W2023590790 modified "2023-10-18" @default.
• W2023590790 title "MOSFET Scaling Trends, Challenges, and Key Associated Metrology Issues Through the End of the Roadmap" @default.
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• W2023590790 doi "https://doi.org/10.1063/1.2062964" @default.
• W2023590790 hasPublicationYear "2005" @default.
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