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- W2023606426 abstract "In this paper, we propose two new techniques to accelerate concurrent fault simulation. In concurrent fault simulation, if detectable faults are increased, then fault lists of primary outputs become empty for almost all input patterns. In our first technique, we introduce simple calculation instead of exact calculation of the fault lists. In these calculations we check whether the fault lists of the signal lines are empty or not. When emptiness checking of all signal lines is done and the fault lists of all primary outputs are empty, then we conclude that no fault can be detected. Parallel processing of input patterns is possible for this emptiness checking. As a result of emptiness checking, if fault lists of some primary outputs prove to be nonempty, then we must calculate the exact fault lists. Our second technique utilizes the information obtained during emptiness checking to decide the set of lines for which the exact fault lists must be calculated. It is confirmed by the experimental results that these techniques accelerate concurrent fault simulation by about 10 times for the ISACS 85 bench mark circuit. © 1998 Scripta Technica. Syst Comp Jpn, 28(12): 53–64, 1997" @default.
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- W2023606426 date "1997-11-15" @default.
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- W2023606426 title "Accelerating concurrent fault simulation by parallel pattern emptiness checking of fault lists" @default.
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- W2023606426 doi "https://doi.org/10.1002/(sici)1520-684x(19971115)28:12<53::aid-scj6>3.0.co;2-c" @default.
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