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- W2023708001 abstract "Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits." @default.
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- W2023708001 title "Graphical approach for multiple valued logic minimization" @default.
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- W2023708001 doi "https://doi.org/10.1117/1.602123" @default.
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