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• W2023716213 abstract "A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process." @default.
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• W2023716213 date "2013-12-01" @default.
• W2023716213 modified "2023-09-27" @default.
• W2023716213 title "A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process" @default.
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• W2023716213 doi "https://doi.org/10.1109/jssc.2013.2278805" @default.
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