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• W2023721041 abstract "Many realisations of multi-operand addition and partial product reduction use (4:2) compressor () as the basic addition or reduction cell. A is functionally equivalent to two cascaded full adders (FAs) in the sum path, where there are four XOR gates along the critical delay path. This is one XOR more than that of conventional realisation of , where no FAs per se are used. However, since the gate level evaluation is not always reliable, we undertake practical simulations and realisations of conventional and double-FA with optimised FAs, which show better result for double-FA realisation. This experience motivated us to study all possible ways of designing s with optimised FAs, where we came up with four new designs. All the proposed and referenced designs are evaluated by HSPICE simulations using NANGATE pre- and post-layout CMOS standard cell library of 45 nm. The results show that latency, power-delay product and device count of our fastest is 9%, 16% and 10% less than that of previous fastest design, respectively. To investigate performance of proposed s in real applications, we implemented five -bit multipliers with over 1300 s. These experiments confirmed our results on isolated simulations." @default.
• W2023721041 created "2016-06-24" @default.
• W2023721041 creator A5001597461 @default.
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• W2023721041 date "2014-01-30" @default.
• W2023721041 modified "2023-10-06" @default.
• W2023721041 title "High-performance CMOS (4:2) compressors" @default.
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• W2023721041 doi "https://doi.org/10.1080/00207217.2014.880133" @default.
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