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• W2023856716 abstract "This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate." @default.
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• W2023856716 date "2008-09-01" @default.
• W2023856716 modified "2023-10-01" @default.
• W2023856716 title "Signal Integrity Enhancement in Digital Circuits" @default.
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• W2023856716 doi "https://doi.org/10.1109/mdt.2008.146" @default.
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