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• W2023874974 abstract "A high-speed, low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32% reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter." @default.
• W2023874974 created "2016-06-24" @default.
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• W2023874974 date "2007-01-01" @default.
• W2023874974 modified "2023-09-25" @default.
• W2023874974 title "High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers" @default.
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• W2023874974 doi "https://doi.org/10.1049/el:20072490" @default.
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