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- W2023985661 abstract "A generalization of a known class of parallel sorting algorithms is presented, together with a new interconnection to execute them. A VLSI implementation is also proposed, and its area-time performance is discussed. It is shown that an algorithm in the class is executable in O(logn) time by a chip occupying O(n2) area. The design is a typical instance of a “hybrid architecture”, resulting from the combination of well-known VLSI networks as the orthogonal trees and the cube-connected-cycles; it also provably meets the AT2=omegan2log2n) lower bound for sorters of n words of length (1+epsilon)logn(epsilon > O)." @default.
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- W2023985661 date "1984-01-01" @default.
- W2023985661 modified "2023-09-25" @default.
- W2023985661 title "A minimum area VLSI network for O(logn) time sorting" @default.
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- W2023985661 doi "https://doi.org/10.1145/800057.808666" @default.
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