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• W2024194297 abstract "Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transistors required to implement single clocked gates. In the verification by simulation, the proposed flip-flops appears to have lesser power consumption and better speed of operation." @default.
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• W2024194297 date "2005-04-01" @default.
• W2024194297 modified "2023-09-23" @default.
• W2024194297 title "DESIGN OF 3-VALUED R-S & D FLIP-FLOPS BASED ON SIMPLE TERNARY GATES" @default.
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• W2024194297 doi "https://doi.org/10.1142/s0218194005002324" @default.
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