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- W2024528067 abstract "In this paper we consider the synthesis of sequential machines by networks of a fixed module with delay. We show that every binary input n state sequential machine has an isomorphic realization using at most p copies of a module with 2r + 1 inputs, where p is the smaller of <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>${2r over 2r - 1} (n^{1+log r^2} + 4n^{1+log r^4)$</tex> and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$r2^[n/r]$</tex> . ([x] is the smallest integer ≧ x.)" @default.
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- W2024528067 date "1969-05-06" @default.
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- W2024528067 title "Uniform Synthesis of Sequential Circuits†" @default.
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- W2024528067 doi "https://doi.org/10.1002/j.1538-7305.1969.tb04263.x" @default.
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