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- W2024706980 abstract "A BiCMOS channelless gate array using 0.5-μm BiCMOS technology is described. To improve the speed and density of the gate array, a novel feedback-type BiCMOS circuit and the channelless architecture were adopted. The plane-type gate array has 54 K cells and can construct a three-input NAND or NOR gate using one of them. The array realizes the high utilization ratio of basic cells using a four-metal-layer wiring technique. If macrocells are used, the density of the chip becomes more than twice that of a plane-type gate array. The gate delay time of 220 ps was simulated using a feedback-type BiCMOS two-input NAND circuit and 0.5-μm BiCMOS devices with a 4-V power supply. This high-performance BiCMOS channelless gate array can be applied to high-speed computers" @default.
- W2024706980 created "2016-06-24" @default.
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- W2024706980 date "1989-01-01" @default.
- W2024706980 modified "2023-09-26" @default.
- W2024706980 title "A 0.5 &mu;m BiCMOS channelless gate array" @default.
- W2024706980 cites W1975493405 @default.
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- W2024706980 doi "https://doi.org/10.1109/cicc.1989.56718" @default.
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