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• W2024951057 abstract "We present a hybrid integration technology platform for the compact integration of best-in-breed VLSI and photonic circuits. This hybridization solution requires fabrication of ultralow parasitic chip-to-chip interconnects on the candidate chips and assembly of these by a highly accurate flip-chip bonding process. The former is achieved by microsolder bump interconnects that can be fabricated by wafer-scale processes, and are shown to have average resistance <1 ohm/bump and capacitance <25fF/bump. This suite of technologies was successfully used to hybrid integrate high speed VLSI chips built on the 90nm bulk CMOS technology node with silicon photonic modulators and detectors built on a 130nm CMOS-photonic platform and an SOI-photonic platform; these particular hybrids yielded Tx and Rx components with energies as low as 320fJ/bit and 690fJ/bit, respectively. We also report on challenges and ongoing efforts to fabricate microsolder bump interconnects on next-generation 40nm VLSI CMOS chips." @default.
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• W2024951057 date "2011-02-10" @default.
• W2024951057 modified "2023-09-26" @default.
• W2024951057 title "Hybrid-integrated silicon photonic bridge chips for ultralow-energy inter-chip communications" @default.
• W2024951057 doi "https://doi.org/10.1117/12.876526" @default.
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