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- W2024956974 abstract "This paper presents a 65-nm CMOS, 1-V, 1.37-pJ/bit optical receiver with embedded equalizer, enabling adaptability to overcome channel losses and component variations. The digitally-controlled continuous-time linear equalizer (CTLE) consists of three cascaded tunable peaking stages offering 16-dB of adjustable low-frequency gain. Optical measurement results with a 30-Gb/s photodetector (PD) show that the receiver achieves 10−12 BER at 30 Gb/s for a 215−1 PRBS input with a −5.6-dBm input sensitivity. Using a lower bandwidth 14-Gb/s PD, the receiver can still reach 30 Gb/s at 10−12 BER with only a 0.6-dB degradation in input sensitivity. These measurement results demonstrate the effectiveness of the proposed receiver and the programmable cascaded CTLE." @default.
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- W2024956974 date "2014-09-01" @default.
- W2024956974 modified "2023-10-03" @default.
- W2024956974 title "A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization" @default.
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- W2024956974 doi "https://doi.org/10.1109/esscirc.2014.6942038" @default.
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