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- W2025559938 abstract "For many years, flight software (FSW) has been developed and verified using real hardware-based software test beds (STBs). Even though the STB presents the best real-time behavior of the FSW, it has a number of drawbacks such as very long delivery time for the target hardware, frequent changes in hardware configurations, and limited concurrent access to the STB. Therefore, software-based satellite simulators have been developed from the start of a project to overcome the restrictions and limitations imposed by the STB. They enable the development of FSW to progress in parallel with developing the target hardware from the initial phase of the project. In this approach, the processor emulator is the essential component of the satellite simulator, but its interpretation-based approach cannot meet the real-time requirements as the clock speed of the emulation target increases. In this paper, we discuss the design and development of a high-performance and cycle-accurate space processor emulator based on a just-in-time (JIT) dynamic binary translation (DBT) scheme. We also present a solution for self-modifying code emulation which is essential for satellite software but has been a limiting factor in the DBT scheme." @default.
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- W2025559938 date "2015-01-01" @default.
- W2025559938 modified "2023-09-23" @default.
- W2025559938 title "A Fast, Cycle-accurate Space Processor Emulator Based on a Dynamic Binary Translator" @default.
- W2025559938 cites W2132071463 @default.
- W2025559938 doi "https://doi.org/10.2322/tjsass.58.170" @default.
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