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- W2025576208 abstract "This paper describes a multi-bit third-order incremental analog-to-digital (ADC) architecture and design considerations to achieve 18-bit resolution. The architecture uses multi-bit quantization in order to increase resolution and reduce the output swing of op-amps. The non-linearity due to the mismatch of unity elements of multi-bit DAC is properly compensated for with Smart-DEM algorithm. This 2+1 incremental architecture achieves 18-bit resolution with a 3-bit quantizer. Simulation results verify the target resolution achieved with 61 clock periods despite a large unity element mismatch (3σ = 0.5%)." @default.
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- W2025576208 date "2014-06-01" @default.
- W2025576208 modified "2023-09-23" @default.
- W2025576208 title "A 2+1 multi-bit incremental architecture using Smart-DEM algorithm" @default.
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- W2025576208 doi "https://doi.org/10.1109/iscas.2014.6865473" @default.
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