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- W2025770906 abstract "In a wireless communications system, a pre-distorter is often used to compensate for the nonlinear distortions that result from operating a power amplifier near the saturation region, thereby improving system performance and increasing the spectral efficiency for the communication channels. This paper presents a new VLSI design for the polynomial digital pre-distorter (DPD). The proposed DPD uses a Coordinate Rotation Digital Computing (CORDIC) processor and a PD process with a fullypipelined architecture. Due to its simple and regular structure, it can be a competitive design when compared to existing polynomial-type and approximated DPDs. Implementing a fifth-order distorter with the proposed design requires only 43,000 logic gates in a 0.35 ㎛ CMOS standard cell library." @default.
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- W2025770906 date "2014-12-30" @default.
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- W2025770906 title "A VLSI Design for Digital Pre-distortion with Pipelined CORDIC Processors" @default.
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- W2025770906 doi "https://doi.org/10.5573/jsts.2014.14.6.718" @default.
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