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- W2026302628 abstract "We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate the highest reported capacitor density of C=1 μF/mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> (=1,000 fF/μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ) and the figure of merit (FOM) C*V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>bd</sub> =11 C/m <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> (V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>bd</sub> is the breakdown voltage). Through-Si vias can be used to combine passive and active die into a single stack. Addition of optical layers to the Bipolar CMOS DMOS (BCD) process allows light detection in the visible and infrared range. 3D package-level integration is illustrated by embedding of multiple active and passive components in one package." @default.
- W2026302628 created "2016-06-24" @default.
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- W2026302628 date "2013-12-01" @default.
- W2026302628 modified "2023-09-26" @default.
- W2026302628 title "3D heterogeneous integration for analog" @default.
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- W2026302628 doi "https://doi.org/10.1109/iedm.2013.6724688" @default.
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