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• W2026327105 abstract "A low-voltage and low-power 50/100-GHz transformer-based phase-locked loop (PLL) is implemented in a 65-nm CMOS technology. Consuming only 14.1 mW from a 0.6/1.2-V supply, the PLL measures phase noise of -90/ -84 dBc/Hz at 100-kHz offset and -94/ -88 dBc/Hz at 1-MHz offset at 49.7/99.4 GHz while occupying a core chip area of 0.39 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . Moreover, with an embedded phase shifter, the PLL output phase can be shifted by a 360 ° range with an average resolution of 3.9 ° and amplitude variation less than ±0.1 dB, which makes it suitable for phased-array transceivers." @default.
• W2026327105 created "2016-06-24" @default.
• W2026327105 creator A5017948476 @default.
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• W2026327105 date "2015-04-01" @default.
• W2026327105 modified "2023-10-03" @default.
• W2026327105 title "Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS" @default.
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• W2026327105 doi "https://doi.org/10.1109/tmtt.2015.2407364" @default.
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