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• W2027009856 endingPage "2038" @default.
• W2027009856 startingPage "2030" @default.
• W2027009856 abstract "A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing standby power at times when only a fraction of the entire memory is utilized. Measurement results from a 64 kb eDRAM test chip in 65 nm CMOS demonstrate the effectiveness of the proposed circuit techniques." @default.
• W2027009856 created "2016-06-24" @default.
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• W2027009856 date "2013-08-01" @default.
• W2027009856 modified "2023-10-13" @default.
• W2027009856 title "A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode" @default.
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• W2027009856 doi "https://doi.org/10.1109/tcsi.2013.2252652" @default.
• W2027009856 hasPublicationYear "2013" @default.
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