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- W2028781127 abstract "A systematic placement algorithm is described for the design of CMOS logic cells. Unlike the other placement algorithms that apply only to NAND/NOR circuits or that are very time consuming, the proposed algorithm applies to any kind of CMOS circuit, and has no restriction as to the NAND/NOR circuits. Furthercmore, it applies to both planar and non-planar circuits. In addition, since a very efficient graph-theoretic approach is used as a constructive algorithm which generates a near optimal initial placement combined with an iterative approach by simulated annealing, an optimum result can be obtained in less time. The layout style of a transistor chain is used which, in conjunction with the optimal synthesized design approach using switching network logic, constitutes a systematic method for the design automation of high-speed VLSI circuits." @default.
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- W2028781127 date "1991-05-01" @default.
- W2028781127 modified "2023-09-22" @default.
- W2028781127 title "Placement algorithm for the optimal synthesized design of CMOS logic cells" @default.
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- W2028781127 doi "https://doi.org/10.1080/00207219108921333" @default.
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