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• W2028930055 abstract "An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm/sup 2/ die size.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
• W2028930055 created "2016-06-24" @default.
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• W2028930055 date "1989-10-01" @default.
• W2028930055 modified "2023-09-27" @default.
• W2028930055 title "A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions" @default.
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• W2028930055 doi "https://doi.org/10.1109/jssc.1989.572608" @default.
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