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- W2029023930 abstract "As very large scale integration (VLSI) packing density increases, the aspect ratio becomes higher. Especially, in the latter part of the large scale integration (LSI) fabrication process both the resolution and the linewidth control of the resist pattern become poor due to the influence of substrate surface topography. A multilayer resist system is one of the solutions of that problem. However, it is not easy to adapt the usual multilayer resist system to the LSI manufacturing process lines because of its complexity and difficulty. This paper will present the capabilities of resist patterning on a substrate having topographic steps produced by both the contrast enhanced layer (CEL) method and a thick resist. We found that optimum focus position depended on the CEL thickness, and the relationship between them was linear. Using this technology resist profiles of 1.0 μm line and space (L&S) in a 5.0 μm thick resist were achieved." @default.
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- W2029023930 date "1992-07-01" @default.
- W2029023930 modified "2023-10-16" @default.
- W2029023930 title "Thick Resist Patterning Using the Contrast Enhanced Layer Method" @default.
- W2029023930 doi "https://doi.org/10.1149/1.2069531" @default.
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