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- W2029121757 abstract "We elaborated a new ultra low-power nanometer circuit design methodology by introducing statistical fluctuations in advanced technology nodes as noise sources causing computational errors. The modeling is performed on sub-50 nm technology node to create a statistical performance metric. The relationship between the probability of error and the circuit noise for a variety of different configurations and of circuit topologies is explored. Input-coupled noise has the dominant effect in terms of error and is analyzed through AC and high-frequency properties of the inverter transfer characteristics. Gate-level implementation of the probabilistic CMOS logic is validated with circuit simulations using a commercial 45-nm SOI CMOS process technology. Using a 32-bit adder where voltages can be scaled from MSB to LSB as an example, simulation results show the power of the technique. A calculation error of 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>−6</sup> , a number quite appropriate for many computational tasks, occurs with a total power reduction of more than 40 %." @default.
- W2029121757 created "2016-06-24" @default.
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- W2029121757 date "2011-06-01" @default.
- W2029121757 modified "2023-09-27" @default.
- W2029121757 title "Inexact computing for ultra low-power nanometer digital circuit design" @default.
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- W2029121757 doi "https://doi.org/10.1109/nanoarch.2011.5941479" @default.
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