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- W2029192160 abstract "In this paper a VLSI implementation of a highly scalable MMSE (Minimum Mean Square Estimator) is presented with the ultimate goal of demonstrating the potential of MMSE as enabler for multi-standard channel estimation. By selecting an appropriate implementation, a complexity reduction of 98% is achieved when compared to Time-Domain Maximum Likelihood Estimation (TDMLE), whereas low power consumption is accomplished by implementing a low-power-mode. The architecture is capable of performing Least Square (LS) estimation and MMSE compliant with 3GPP LTE (Long Term Evolution), IEEE 802.11n (WLAN), and DVB-H (Digital Video Broadcast for Handheld Devices), The estimator is synthesized using a 65nm low-leakage high-threshold standard-cell CMOS library. The design occupies an area of 0.169 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , is capable of running upto 250 MHz, providing a throughput of 78M estimates/second. Simulations under a typical LTE reception show that the implementation dissipates 4.9μW per sample." @default.
- W2029192160 created "2016-06-24" @default.
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- W2029192160 date "2011-10-01" @default.
- W2029192160 modified "2023-09-26" @default.
- W2029192160 title "Highly scalable implementation of a robust MMSE channel estimator for OFDM multi-standard environment" @default.
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- W2029192160 doi "https://doi.org/10.1109/sips.2011.6088995" @default.
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