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- W2029473641 abstract "Nonbinary LDPC codes have shown superior performance, but decoding nonbinary codes is complex, incurring a long latency and a much degraded throughput. We propose a low-latency variable processing node by a skimming algorithm, together with a low-latency extended min-sum check processing node by prefetching and relaxing redundancy control. The processing nodes are jointly designed for an optimal pipeline schedule. This low-latency, high-throughput architecture is applied to a class of high-performance (2, d <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>c</sub> )-regular nonbinary LDPC codes constructed based on their binary images. A conflict-free memory is proposed to resolve data hazards caused by the non-structured nature of these codes. A complete (2, 4)-regular, (960, 480) GF(64) nonbinary LDPC decoder is demonstrated on a Xilinx Virtex-5 FPGA. The decoder delivers an excellent error-correcting performance at a 9.76 Mb/s coded throughput, representing a significant improvement of state-of-the-art extended min-sum decoder implementations." @default.
- W2029473641 created "2016-06-24" @default.
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- W2029473641 date "2012-05-01" @default.
- W2029473641 modified "2023-09-27" @default.
- W2029473641 title "High-throughput architecture and implementation of regular (2, d<inf>c</inf>) nonbinary LDPC decoders" @default.
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- W2029473641 doi "https://doi.org/10.1109/iscas.2012.6271844" @default.
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