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- W2030723372 abstract "Timing slacks of a synthesized design can be used to identify some local networks for embedding watermark information to achieve the goal of IP protection. The identification of suitable local networks plays a key role to ensure that the watermarked design can still meet the constraints from the original synthesized result. We propose a method to select the kernels according to the anticipatory global effect caused by their remapping. The design is updated progressively by retaining or remapping the newly found kernel according to the stego-signature bit to be embedded before seeking for the next kernel. We have tested this method on a set of MCNC combinational benchmarks. Experimental results show that for as long as the original design size is not too small, our method can extract enough kernels for watermark insertion with trivial overhead and guaranteed timing convergence." @default.
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- W2030723372 date "2006-12-01" @default.
- W2030723372 modified "2023-10-12" @default.
- W2030723372 title "Kernel Extraction for Watermarking Combinational Logic Networks" @default.
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- W2030723372 doi "https://doi.org/10.1109/apccas.2006.342262" @default.
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