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• W2031964120 abstract "Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We present a 3D double stacked 4Gb MLC NAND flash memory device with shared bitline structure, with a cell size of 0.0021mum <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> /bit per unit feature area. The device is designed to support 3D stacking and fabricated by S3 and 45nm floating-gate CMOS technologies." @default.
• W2031964120 created "2016-06-24" @default.
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• W2031964120 date "2008-02-01" @default.
• W2031964120 modified "2023-09-26" @default.
• W2031964120 title "A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure" @default.
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• W2031964120 doi "https://doi.org/10.1109/isscc.2008.4523281" @default.
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