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- W2032133346 abstract "This paper presents a new high speed 5-2 compressor. It is designed based on a new truth table which leads to a simple structure. Also, the driving problems are reduced. Due to the similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays and the power dissipation is decreased. Furthermore, by use of full swing logics, the speed of cascaded operations is enhanced. The latency of proposed design is 440ps." @default.
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- W2032133346 date "2013-01-01" @default.
- W2032133346 modified "2023-10-16" @default.
- W2032133346 title "CMOS implementation of a new high speed 5-2 compressor for parallel accumulations" @default.
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- W2032133346 doi "https://doi.org/10.1587/elex.10.20130364" @default.
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