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• W2032655623 abstract "Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time." @default.
• W2032655623 created "2016-06-24" @default.
• W2032655623 creator A5018000834 @default.
• W2032655623 creator A5062809059 @default.
• W2032655623 date "2014-08-01" @default.
• W2032655623 modified "2023-09-24" @default.
• W2032655623 title "Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs" @default.
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• W2032655623 doi "https://doi.org/10.4218/etrij.14.0113.1204" @default.
• W2032655623 hasPublicationYear "2014" @default.
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